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HTG12B0 4-Bit Microcontroller
Features
* * * * * * * * *
Operating voltage: 2.4V~3.6V Eight input lines Eight input/output lines Five working registers 4K 8 4 program ROM 128 4 8 (4096) bits data memory RAM Sound effect circuit 40 segment 16 common, 1/4 bias LCD driver LCD output is fixed at 4.4V
* * * * * * *
RC oscillator & 32768Hz crystal oscillator 8-bit timer with internal or external clock source Internal timer overflow Up to 4ms instruction cycle with 1MHz system clock One level subroutine nesting Halt feature reduces power consumption 8-bit table read instruction
General Description
The HTG12B0 is a processor from HOLTEKs 4-bit stand-alone single chip microcontroller specially designed for LCD display and time piece product applications. It is ideally suited for multiple LCD for time piece low power applications among which are calculators, scales, calendar and hand held LCD products.
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HTG12B0
Block Diagram
S ta c k
T im e r ALU PA
TM CLK
X IN XOUT OSCI OSCO RES TEST1 TEST2 T1D T512 VDD VSS In s tr u c tio n D ecoder ROMB RAMB LCDC C o n tro l & T im in g C ir c u it
P ro g ra m C o u n te r
PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3
ACC PB
ROM R0 R1 R2 R3 R4 PS PS0 PS1 PS2 PS3 PM0 PM1 PM2 PM3
PM
T e m p o ra ry D a ta R A M D is p la y D a ta R A M Sound E ffe c t BZ BZ VLC VLC VLC VLC 2 3 4 1
VOU VOU VOU VOU
T1 T2 T3 T4 L C D D r iv e r
Note: ACC: Accumulator R0~R4: Working registers ROMB: ROM bank switch RAMB: RAM bank switch LCDC: LCD control register PA, PB: I/O ports PS, PM: Input ports
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SEG0
SEG1
SEG 38
SEG 39
COM0
COM1
COM2
COM3
CO M 15
HTG12B0
Pad Assignment
SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 TEST1
92
TEST2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
T512
93
PM3
94
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
PM2
1 2
71
SEG 19
PM1 PM0 PS3
3 4 5 6 7 8 9
70 69
SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29 SEG 30 SEG 31 SEG 32 SEG 33
PS2 PS1 PS0 TM CLK RES PB3 PB2 PB1 PB0 PA0 PA1 PA2 PA3 T1D BZ BZ VDD OSCO OSCI XOUT X IN VSS
68 67
66 10 65
11 64 12 63
13
62 61
14
(0 , 0 )
60
15
59
16 58 17 57
18
56 55 19 20 21 54 53
SEG 34 SEG 35 SEG 36 SEG 37 SEG 38 SEG 39 COM0
22 23 24 25 26 50 52 51
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
* The IC substrate should be connected to VSS in the PCB layout artwork.
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VLC1
VLC2
VLC3
VLC4
VOUT1
VOUT2
Chip size: 3060 5140 (mm)2
VOUT3
VOUT4
CO M 15
CO M 14
CO M 13
CO M 12
CO M 11
CO M 10
COM8 COM9
COM7
COM6
COM5
COM4
COM3
COM2
COM1
HTG12B0
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1304.07 -1304.07 -1318.48 -1355.04 -1355.04 -1355.04 -1355.04 -1343.84 -1315.52 -1195.52 -1075.52 -955.52 -835.52 -715.52 Y 2163.72 2043.72 1923.72 1803.72 1683.72 1563.72 1443.72 1323.72 1203.72 998.68 749.88 515.16 266.36 31.64 -217.16 -451.88 -700.68 -935.40 -1189.85 -1344.25 -1483.72 -1630.76 -1750.76 -1885.00 -2005.00 -2164.44 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 Pad No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 X 1204.48 1324.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 Y -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2177.80 -1889.00 -1769.00 -1480.20 -1360.20 -1071.40 -951.40 -662.60 -542.60 -253.80 -133.80 155.00 275.00 563.80 683.80 Pad No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 X 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1327.44 1207.44 1087.44 967.44 847.44 727.44 607.44 487.44 367.44 247.44 127.44 7.44 -112.56 -232.56 -352.56 -472.56 -592.56 -712.56 -832.56 -952.56 -1072.56 -1192.56 -1312.56 Unit: mm Y 972.60 1092.60 1381.40 1501.40 1790.20 1910.20 2199.00 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28
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HTG12B0
Pad Description
Pad No. 4~7 94, 1~3 8 9 Pad Name PS3~PS0 PM3~PM0 TMCLK RES I/O I Mask Option Description
Pull-high or None. Input pins for input only Note 2 Pull-high or None. Note 4 3/4 Input for TIMER clock TIMER can be clocked by an external clock or an internal frequency source. Input to reset an internal LSI Reset is active on logical low level.
I I
17~14 10~13 19, 20 21 23 22 25 24 26 27~30 31~34 35~50 51~90 93 18 92 91
PA3~PA0 PB3~PB0 BZ, BZ VDD OSCI OSCO XIN XOUT VSS VLC1~VLC4 VOUT1~VOUT4 COM15~COM0 SEG39~SEG0 T512 T1D TEST1 TEST2
I/O
CMOS or NMOS with Pull-high or Input/output pins None. Note 3 Note 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Sound effect outputs Positive power supply An external resistor between OSCI and OSCO is needed for internal system clock. 32768Hz crystal oscillator for time base, LCD clock Negative power supply, GND LCD system power 1/4 bias generated LCDsystemvoltageboostercondenserconnecting terminal Output for LCD panel common plate LCD driver outputs for LCD panel segment For test mode only TEST1 and TEST2 are left open when the chip is in normal operation (with an internal pull-high resistor).
O I I O I O I I I O O O O I I
Note: 1. The system clock provides six different sources selectable by mask option to drive the sound effect clock. If the Holtek sound library is used, only 128K and 64K are acceptable. 2. Each bit of ports PM, PS can be a trigger source of the HALT interrupt, selectable by mask option. 3. Each bit of ports PA, PB can be selected as CMOS for output pin only, or as NMOS for I/O pin with pull-high resistor or none by mask option. 4. 14 internal clock sources can be selected by mask option to drive TMCLK. Note that TMCLK should not be connected to a pull high resistor if an internal source is used.
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HTG12B0
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Storage Temperature.................-50C to 125C Input Voltage ......................VSS-0.3 to VDD+0.3 Operating Temperature ..................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 RPH VLCD Parameter Operating Voltage Operating Current Standby Current, (fSYS OFF and RTC ON, LCD ON) Input Low Voltage Input High Voltage PA, PB, BZ and BZ Output Sink Current PA, PB, BZ and BZ Output Source Current Segment Output Sink Current Segment Output Source Current Pull-high Resistor VLCD Output Voltage Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 No load, fSYS=512kHz Halt mode 3/4 3/4 VOL=0.3V VOH=2.7V VOL=0.44V VLCD=4.4V VOH=4.0V VLCD=4.4V PS, PM, RES, TMCLK 3/4 Min. 2.4 3/4 3/4 0 0.8VDD 1.5 -0.5 100 30 50 3.96 Typ. 3 200 10 3/4 3/4 3 -1 200 60 100 4.4
Ta=25C Max. 3.6 300 15 0.2VDD VDD 3/4 3/4 3/4 3/4 150 4.84 Unit V mA mA V V mA mA mA mA kW V
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HTG12B0
A.C. Characteristics
Symbol fSYS tCY fTIMER tRES fSOUND Parameter System Clock Cycle Time Timer I/P Frequency (TMCLK) Reset Pulse Width Sound Effect Clock Test Conditions VDD 3V 3V 3V 3/4 3/4 Conditions R=620kW~51kW fSYS=1MHz 3/4 3/4 3/4 Min. 128 3/4 0 5 3/4 Typ. 3/4 4 3/4 3/4 *64 or 128 Max. 1000 3/4 1000 3/4 3/4 Ta=25C Unit kHz ms kHz ms kHz
*: Only these two clocking signal frequencies are supported by the Holtek sound library.
Functional Description
Program counter - PC This counter addresses the program ROM and is arranged as a 12-bit binary counter from PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter counts with an increment of 1 or 2 with each execution of an instruction. When executing the jump instruction (JMP, JNZ, JC, JTMR,...), a subroutine call, initial reset, internal interrupt, RTC interrupt or returning from a subroutine, the program counter is loaded with the corresponding instruction data as shown in the table. Note: P0~P11: Instruction code @: PC11 keeps current value S0~S11: Stack register bits ROMB0 and ROMB1 are set to 0 at power on reset. Program memory - ROM The program memory is the executable memory and is arranged in a 40968-bit format. There are four banks for program memory in HTG12B0, each bank shown in the figure can be switched by assigning ROMB0 and ROMB1 (bit0 and bit1 of ROMB). ROMB is the ROM bank pointer and can be written only by executing MOV ROMB, A instruction. Bit 2 and bit 3 of ROMB are unused bits. The address is specified by the program counter (PC). Four special locations are reserved as described next.
7 * Location 000H: (Bank 0)
Activating the processor RES pin causes the first instruction to be fetched from location 0.
000H 004H 008H 00BH Page N F00H FFFH lo o k - u p ta b le R e s e t in itia l p r o g r a m T im e r in te r r u p t s u b r o u tin e RTC in te r r u p t s u b r o u tin e P ro g ra m ROM Bank 0
P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its
Program memory ROMB=XX00B
000H 004H 008H 00BH Page N F00H FFFH lo o k - u p ta b le T im e r in te r r u p t s u b r o u tin e RTC in te r r u p t s u b r o u tin e P ro g ra m ROM Bank 1
P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its
Program memory ROMB=XX01B
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HTG12B0
* Location 004H: (Bank 0~3)
Contains the timer interrupt resulting from a TIMER overflow. If the interrupt is enabled, the CPU begins execution at location 004H.
* Location 008H: (Bank 0~3)
In the execution of an instruction, the program counter is added before the execution phase, so careful manipulation of READ MR0A and READ R4A is required in the page margin.
000H 004H 008H 00BH Page N F00H FFFH lo o k - u p ta b le T im e r in te r r u p t s u b r o u tin e RTC in te r r u p t s u b r o u tin e P ro g ra m ROM Bank 2
Activating the RTC of the processor with the interrupts enabled causes the program to jump to this location.
* Locations n00H to nFFH: (Bank 0~3)
Each page in the program memory consists of 256 bytes. This area from n00H to nFFH and F00H to FFFH can be used as a look-up table. Instructions such as READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or to ACC and a data memory address specified by the register pair R1,R0. However as R1,R0 can only store 8 bits, these instructions cannot fully specify the full 12 bit program memory address. For this reason a jump instruction should first be used to place the program counter in the right page. The above instructions can then be used to read the look up table data. Note that the page number n must be greater than zero since some locations in page 0 are reserved for specific usage. This area may function as normal program memory. The program memory mapping is shown in the diagram.
Mode Initial reset Internal interrupt RTC interrupt Jump, call instruction Conditional branch PC13 PC12 PC11 PC10 0 0 0 P11 @ S11 0 0 0 P10 P10 S10 PC9 0 0 0 P9 P9 S9 PC8 0 0 0 P8 P8 S8
P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its
Program memory ROMB=XX10B
000H 004H 008H 00BH Page N F00H FFFH lo o k - u p ta b le T im e r in te r r u p t s u b r o u tin e RTC in te r r u p t s u b r o u tin e P ro g ra m ROM Bank 3
P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its
Program memory ROMB=XX11B
Program Counter PC7 0 0 0 P7 P7 S7 PC6 0 0 0 P6 P6 S6 PC5 0 0 0 P5 P5 S5 PC4 0 0 0 P4 P4 S4 PC3 0 0 1 P3 P3 S3 PC2 0 1 0 P2 P2 S2 PC1 0 0 0 P1 P1 S1 PC0 0 0 0 P0 P0 S0
ROMB1 ROMB0 ROMB1 ROMB0 ROMB1 ROMB0 ROMB1 ROMB0 ROMB1 ROMB0
Return from ROMB1 ROMB0 subroutine
Program memory
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HTG12B0
RAM Bank 0 (R A M B = X 0 0 0 B ) 00H 7FH T e m p o ra ry D a ta A re a (1 2 8 x 4 ) 4 b its 00H 7FH RAM Bank 1 (R A M B = X 0 0 1 B ) T e m p o ra ry D a ta A re a (1 2 8 x 4 ) 4 b its 00H 7FH RAM Bank 7 (R A M B = X 1 1 1 B ) T e m p o ra ry D a ta A re a (1 2 8 x 4 ) 4 b its
Temporary data memory Stack register The stack register is a group of registers used to save the contents of the program counter (PC) and is arranged into 13 bits 1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or an interrupt routine which is signaled by a return instruction, RET or RETI restore the program counter to its previous value from stack register. Executing RETI instruction will restore the carry flag from the stack register, but RET does not. Working registers - R0, R1, R2, R3, R4 There are five working registers (R0, R1, R2, R3, R4) usually used to store the frequently accessed intermediate results. Using the instructions INC Rn and DEC Rn the working registers can increment (+1) or decrement (-1). The JNZ Rn (n=0, 1, 4) instruction makes efficient use of the working registers as a program loop counter. Also the register pairs R0,R1 and R2,R3 are used as a data memory pointer when the memory transfer instruction is executed. Data memory - RAM The static data memory (RAM) is arranged in 1284-bit format and is used to store data. All of the data memory locations are indirectly addressable through the register pair R1,R0 or R3,R2; for example MOV A,[R3R2] or MOV [R3R2],A. There are two areas in the data memory, the temporary data area and display data area. Access to the temporary data area is from 00H to
9 September 8, 1999
7FH of RAM bank 0~RAM bank 7. Access to the display data area is from B0H to FFH of LCD bank 0 and bank 1. There are eight banks for the temporary data memory in HTG12B0, each bank shown in the figure can be switched by assigning RAMB0~RAMB2 (bit 0~bit 2 of RAMB). RAMB is the RAM bank pointer and can be written only by executing MOV RAMB, A instruction. Bit 3 of RAMB is unused bit. Each bank maps to different area of the data memory. There are two banks for displaying the data memory, each bank can be switched by the assignment of LCDC0 (bit 0 of LCDC). LCDC is a control register for LCD application and can be written only by executing MOV LCDC, A instruction. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals.
LCD Bank 0 (L C D C = X X X 0 B ) B0H FFH D is p la y D a ta A r e a (8 0 x 4 ) 4 b its LCD Bank 1 (L C D C = X X X 1 B ) B0H FFH D is p la y D a ta A r e a (8 0 x 4 ) 4 b its
Display data memory
HTG12B0
The locations between the temporary and display data areas are undefined and cannot be used. Accumulator - ACC The accumulator is the most important data register in the processor. It is one of the sources of input to the ALU and the destination of the results of the operations performed in the ALU. Data to and from the I/O ports and memory also passes through the accumulator. Arithmetic and logic unit - ALU This circuit performs the following arithmetic and logic operations ...
* Add with or without carry * Subtract with or without carry * AND, OR, Exclusive-OR * Rotate right, left through carry * BCD decimal adjust for addition * Increment, decrement * Data transfers * Branch decisions
start the timer, load the counter with the value XXH and then issue a TIMER ON instruction. Note that XX is the desired start count immediate value of the 8 bits. Once the Timer/Counter is started it increments to a maximum count of FFH and then overflows to zero (00H). It then continues to count until stopped by a TIMER OFF instruction or a reset. The increment from the maximum count of FFH to a zero (00H) triggers a timer flag TF and an internal interrupt request. The interrupt may be enabled or disabled by executing the EI and DI instructions. If the interrupt is enabled, the timer overflow will cause a subroutine call to location 4. The state of the timer flag can also be tested with the conditional jump instruction JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed. If an internal source is used, the frequency is determined by the system clock and the parameter n as defined in the equation. The frequency of the internal frequency source can be selected by mask option. system clock Frequency of TIMER clock = 2n where n=0, 1, 2... 3 selectable by mask option. RTC There is a real time clock (RTC) function implemented on the HTG12B0. The RTC function is used to generate an accurate time period. The RTC circuit clock source comes from the 32768Hz crystal oscillator. The block diagram is shown as follows.
X 't a l 3 2 7 6 8 H z
The ALU not only outputs the results of data operations, but also sets the status of the carry flag (CF) in some instructions. Timer/counter The HTG12B0 contains a programmable 8-bit count-up counter which can be used to count external events or used as a clock to generate an accurate time base. If the 8-bit timer clock is supplied by an external source from pin TMCLK, synchronization problems may occur when reading the data from the timer. It is therefore recommended that the timer is stopped before retrieving the data. The 8-bit counter will increment on the rising edge of the clock whether it is internally or externally generated. The Timer/Counter may be set and read with software instructions and stopped by a hardware reset or a TIMER OFF instruction. To re10
1 128
1
2
M
n
,n=0~7
a s k O p tio n
In te rru p t
The output of RTC can be selected by mask option. 256 , n=0~7 Frequency of RTC output = 2n The RTC output is used to generate an interrupt signal.
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HTG12B0
Interrupt The HTG12B0 provides both TIMER and RTC interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. When the RTC is activated during enable interrupt mode and the program is not within a CALL subroutine, this causes a subroutine call to location 8 and reset the interrupt latch. Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine, the TIMER interrupt is activated. This cause a subroutine call to location 4 and resets the timer flag. If both TIMER and RTC interrupts arrive at the same time, the RTC one will be serviced first. When running under a CALL subroutine or DI the interrupt acknowledge is on hold until the RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable results may occur. If within a CALL subroutine both TIMER and RTC interrupt occur, no matter what order they arrive in, the RTC interrupt will be serviced first after leaving the CALL subroutine. This also applies if the two interrupt arrive at the same time. The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed. Initial reset The HTG12B0 provides a RES pin for system initialization. This pin is equipped with an internal pull high resistor and in combination with an external 0.1m~1mF capacitor, it provides an internal reset pulse of sufficient length to guarantee a reset to all internal circuits. If the reset pulse is generated externally, the RES pin must be held low at least 5ms. When RES is active, the internal block will be initialized as shown below: PC TIMER Timer flag SOUND Output port A LCD output ROMB RAMB LCDC HALT This is a special feature of the HTG12B0 to interrupt the chips normal operation and reduce power consumption. When a HALT is executed the following happens ...
* The system clock will be stopped * The contents of the on-chip RAM and regis-
000H Stop Reset (low) Sound off and One sing mode High (or floating state) Enable XX00B X000B 1100B
BZ and BZ output Low level
ters remain unchanged
* RTC oscillator keeps on running * BZ and BZ maintain low level output
The system can leave the HALT mode through initial reset or RTC interrupt or wake-up from the following entry of program counter value. Initial reset: 00H Wake-up: next address of the HALT instruction
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HTG12B0
When the halt status is terminated by the RTC interrupt, the following procedure takes place: Case 1: If the system is in an interrupt-disable state before entering the halt state:
* The system will be awakened and returns to
Holteks sound library supports only sound clock frequency of 128K or 64K. To use Holteks sound library the proper system clock and mask option should be selected. LCD display memory As mentioned in the data memory section, the LCD display memory is embedded in the data memory. It can be read and written to in the same way as normal data memory. The figure illustrates the mapping between the display memory and LCD pattern for the HTG12B0. There is an ON/OFF switch for display controlled by bit 3 of LCDC (LCDC 3). The corresponding bit of the LCDC 3 represents ON or OFF of display of LCD display memory. The LCD display module may have any form as long as the number of commons does not exceed 16 and the number of segments is not over 40.
D IS P L A Y M E M O R Y COM 0 0 1 1 2 2 3 3 FEH FCH FAH F8H B4H B2H B0H B IT
the main program instruction following the HALT command. tem receives an enable interrupt command by which the RTC interrupt will be serviced.
* The RTC interrupt will be held until the sys-
Case 2: If the system is in an interrupt enable state:
* The RTC interrupt will awake the system and
execute the RTC interrupt subroutine.
In the HALT mode, each bit of ports PM, PS, can be used as wake-up signal by mask option to wake-up the system. This signal is active in low-going transition. Sound effects The HTG12B0 includes sound effect circuitry which offers up to 16 sounds with 3 tones, boom and noise effects. Holtek supports a sound library including melodies, alarms, machine guns etc.. If the instruction SOUND A is executed, the specified sound begins. Each time SOUND OFF is executed, it terminates the singing sound immediately. There are two singing modes, SONE mode and SLOOP mode activated by SOUND ONE and SOUND LOOP. In SONE mode the specified sound plays only once. In the SLOOP mode the specified sound keeps re-playing.
FFH 4 5 6 7
FDH
FBH
F9H
B5H
B3H
B1H 0 1 2 3
Since sounds 0~11 contain 32 notes and sounds 12~15 include 64 notes the latter possesses better sound than the former. The frequency of the sound effect circuit can be selected by mask option. system clock Frequency of sound effect circuit = 2m ...where m=0,1,2,3,4,5.
SEGMENT
0
1
2
3
37
38
39
LCD display memory (LCDC0=0)
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HTG12B0
D IS P L A Y M E M O R Y COM 8 9 10 11 3 2 1 FEH FCH FAH F8H B4H B2H B0H B IT 0
* System clock
Frequency of LCD clock = ....where n=0~5
f SYS 64 Hz 2n
LCD driver output can be enabled or disabled by setting LCDC 3 without the influence of the related memory condition. LCD driver output is enabled by setting LCDC3 as 1, and disabled by setting LCDC 3 as 0. Register Bit No.
0 1 2 3
FFH 12 13 14 15
FDH
FBH
F9H
B5H
B3H
B1H
Function Select LCD bank 0=Bank 0 (Com0~7) 1=Bank 1 (Com8~15) Select LCD clock source 0=RTC OSC (32768Hz) 1=System clock PM3 edge latch control bit 1=Enabled 0=Disabled Control LCD display 0=OFF 1=ON
0
1 LCDC 2
SEGMENT
0
1
2
3
37
38
39
LCD display memory (LCDC0=1) LCD driver output All of the LCD segments are random after an initial clear. The bias voltage circuits of the LCD display is built-in and no external resistor is required. The output number of the HTG12B0 LCD driver is 4016 which can directly drive an LCD with 1/16 duty cycle and 1/4 bias. The frequency of the LCD driving clock source can be selected from RTC OSC or system clock by accessing bit 1 of LCDC. There are many frequency division of the LCD clock which can be selected by mask option either from RTC OSC or system clock.
* RTC OSC
3
LCDC Register An example of an LCD driving waveform (1/16 duty and 1/4 bias) is shown below.
64H z 1 1024H z VL 3 /4 V L C O M 0 2 /4 V L 1 /4 V L G VL 3 /4 V L C O M 1 2 /4 V L 1 /4 V L G VL 3 /4 V L S E G 0 2 /4 V L 1 /4 V L G CD CD CD CD ND CD CD CD CD ND CD CD CD CD ND 2 3 13 14 15 1 2 3 4 5
Frequency of LCD clock = ....where n=0~7
16384 Hz 2n
VLCD is fixed at 4.4V when VDD is from 2.4V to 3.6V.
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HTG12B0
Oscillator
V
DD
Only one external resistor is required for the HTG12B0 system clock. The system clock is also used as the reference signal of the sound effect clock or internal frequency source of the TIMER. Another crystal oscillator is needed for use as the reference signal of the LCD driving clock and RTC interrupt clock source. A machine cycle consists of a sequence of 4 states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4ms if the system frequency is up to 1MHz.
OSCI R OSCO XOUT X IN 3 2 .7 6 8 k H z
W a k e -u p P u ll- h ig h m ask o p tio n W a k e -u p m ask o p tio n R e a d c o n tro l
In te rn a l b u s
Input ports PS, PM PM3 has a falling edge latch function selected by mask option. Once the falling edge signal is latched, it will remain in its state until the clear instruction is executed by setting bit 2 of LCDC from high to low. Input/output port - PA, PB PA and PB can be used for input/output or output operation by selecting NMOS or CMOS mask option respectively, and each bit can be configured with or without pull-high resistor when the NMOS is selected. If the NMOS is selected, it should be noted that, before reading, data from pads should output 1 to the related bits to disable the NMOS device.
V
DD
RC and RTC oscillator Interfacing The HTG12B0 microcontrollers communicate with the outside world through two input pins PS and PM and two output pins PA and PB. Input ports - PS, PM All of the ports can have internal pull high resistors determined by mask option. Every bit of the input ports PS and PM can be specified as a trigger source for waking up the HALT interrupt by mask option. A high to low transition on one of these pins will wake up the device from a HALT status.
P u ll- h ig h In te rn a l b u s M a s k o p tio n M a s k o p tio n Q D CK Q
R e a d c o n tro l
Input/output port PA, PB
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Mask options HTG12B0 provides the following mask option for different applications.
* Each bit of input ports PS, PM with pull-high * Six kinds of sound clock frequencies:
fSYS/2m, m=0, 1, 2, 3, 4, 5
* There are eight kinds of RTC interrupt fre-
resistor
quencies. RTC interrupt frequency=256/2n Hz, n=0~7.
* Each bit of input ports PS, PM function as
* LCD clock source division:
HALT wake-up trigger.
* Each bit of input/output port PA, PB with
CMOS or NMOS with pull-high or none.
* 8-bit programmable TIMER with internal or
If RTC OSC is selected, the frequency of LCD clock=16384/2n Hz, n=0~7. If system clock is selected, the frequency of f 64 Hz, n=0~5. LCD clock= SYS n 2
external frequency sources. There are 14 internal frequency sources which can be selected as a clocking signal. If using internal frequency sources as clocking signal TMCLK cannot connect with pull-high resistor.
* PM3 falling edge latch function.
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HTG12B0
Application Circuits
COM0 COM1 L Pa (1 /4 1 /1 6 CO M 15 SEGMENT OUTPUT PS0 PS1 PS2 PS3 IN P U T PORT X40 CD tte rn B ia s , D u ty )
PA0 PA1 PA2 PA3 PM0 PM1 PM2 PM3
I/O PORT
IN P U T PORT
06/
*
BZ BZ
P ie z o B uzzer 0 .1 m F
R*
OSCI OSCO
RES VOUT1
VOUT2 VOUT3 VOUT4 VLC 1 VLC 2 VLC 3 VLC 4
X 'ta
l
X IN XOUT I/O PORT
PB0 PB1 PB2 PB3
R * : D e p e n d s o n th e r e q u ir e d s y s te m c lo c k fr e q u e n c y . ( R = 6 2 0 k W ~ 5 1 k W , a t V X 't a l: R e a lt im e c lo c k f r e q u e n c y . ( X 't a l= 3 2 7 6 8 H z )
DD
=3V)
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HTG12B0
Instruction Set Summary
Mnemonic Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment and Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV ROMB, A MOV RAMB, A MOV LCDC, A MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH MOV ACC to ROMB MOV ACC to RAMB MOV ACC to LCDC Move register to ACC, n=0~4 Move ACC to register, n=0~4 Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Increment ACC Increment register, n=0~4 Increment data memory Increment data memory Decrement ACC Decrement register, n=0~4 Decrement data memory Decrement data memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition 1 1 1 1 2 2 1 1 1 1 1 2 2 1
O O O O O O O
Description
Byte
Cycle
CF
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Mnemonic Rotate RL A RLC A RR A RRC A Input & Output IN A,Pi OUT Pi,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Table Read READ R4A READ MR0A READF R4A READF MR0A Read ROM code of current page to R4 and ACC Read ROM code of current page to M(R1,R0), ACC Read ROM code of page F to R4 and ACC Read ROM code of page F to M(R1,R0), ACC 1 1 1 1 2 2 2 2 3/4 3/4 3/4 3/4 Set 8 bits immediate data to TIMER Set TIMER start counting Set TIMER stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to high nibble of TIMER 2 1 1 1 1 1 1 2 1 1 1 1 1 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation 1 1 1 1 1 1 1 1 1 1 0 1 3/4 3/4 3/4 Subroutine call Return from subroutine or interrupt Return from interrupt service routine 2 1 1 2 1 1 3/4 3/4 O Jump unconditionally Jump on carry=1 Jump on carry=0 Jump on timer overflow Jump on ACC bit n=1 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Input port-i to ACC ,port-i=PM, PS, PA, PB Output ACC to port-i, port-i=PA, PB 1 1 1 1 3/4 3/4 Rotate ACC left Rotate ACC left through carry Rotate ACC right Rotate ACC right through carry 1 1 1 1 1 1 1 1
O O O O
Description
Byte
Cycle
CF
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Mnemonic Sound Control SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT Enter power down mode 2 2 3/4 Activate SOUND channel with ACC Turn on SOUND one cycle Turn on SOUND repeat cycle Turn off SOUND 1 1 1 1 1 1 1 1 3/4 3/4 3/4 3/4 Description Byte Cycle CF
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Instruction Definition
ADC A,[R1R0] Machine Code Description Operation ADD A,XH Machine Code Description Operation ADD A,[R1R0] Machine Code Description Operation AND A,XH Machine Code Description Operation AND A,[R1R0] Machine Code Description Operation AND [R1R0],A Machine Code Description Operation Add data memory contents and carry to accumulator 00001000 The contents of the data memory addressed by the register pair R1,R0 and the carry are added to the accumulator. Carry is affected. ACC ACC+M(R1,R0)+C Add immediate data to accumulator 01000000 ACC ACC+XH Add data memory contents to accumulator 00001001 The contents of the data memory addressed by the register pair R1,R0 is added to the accumulator. Carry is affected. ACC ACC+M(R1,R0) Logical AND immediate data to accumulator 01000010 0000dddd Data in the accumulator is logically AND with the immediate data specified by code. ACC ACC AND XH Logical AND accumulator with data memory 00011010 Data in the accumulator is logically AND with the data memory addressed by the register pair R1,R0. ACC ACC AND M(R1,R0) Logical AND data memory with accumulator 00011101 Data in the data memory addressed by the register pair R1,R0 is logically AND with the accumulator M(R1,R0) M(R1,R0) AND ACC 0000dddd The specified data is added to the accumulator. Carry is affected.
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CALL address Machine Code Description Operation CLC Machine Code Description Operation DAA Machine Code Description Subroutine call 1111aaaa aaaaaaaa The program counter bits 0-11 are saved in the stack. The program counter is then loaded from the directly-specified address. Stack PC+2 PC address Clear carry flag 00101010 The carry flag is reset to zero. C0 Decimal-Adjust accumulator 00110110 The accumulator value is adjusted to the BCD (Binary Code Decimal) code, if the contents of the accumulator is greater, then 9 or C (Carry flag) is one. If ACC>9 or CF=1 then ACC ACC+6, C 1 else ACC ACC, C C Decrement accumulator 00111111 Data in the accumulator is decremented by one. Carry flag is not affected. ACC ACC-1 Decrement register 0001nnn1 Data in the working register Rn is decremented by one. Carry flag is not affected. Rn Rn-1; Rn=R0, R1, R2, R3, R4, for n=0,1,2,3,4 Decrement data memory 00001101 Data in the data memory specified by the register pair R1,R0 is decremented by one. Carry flag is not affected. M(R1, R0) M(R1,R0)-1
Operation
DEC A Machine Code Description Operation DEC Rn Machine Code Description Operation DEC [R1R0] Machine Code Description Operation
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DEC [R3R2] Machine Code Description Operation DI Machine Code Description EI Machine Code Description HALT Machine Code Description Operation IN A,Pi Machine Code Description Operation INC A Machine Code Description Operation INC Rn Machine Code Description Operation Decrement data memory 00001111 Data in the data memory specified by the register pair R3, R2 is decremented by one. Carry flag is not affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00100101 00000011 Internal time-out interrupt and external interrupt are disabled. Enable interrupt 00100101 00000010 Internal time-out interrupt and external interrupt are enabled. Halt system clock 00110111 PC (PC)+1 Input port to accumulator 00101100 00110010 PA PM 01001000 00110011 PB PS 00111110 Turn off system clock, and enter power down mode.
The data on port Pi is transferred to the accumulator. ACC Pi; Pi=PA, PB, PM or PS Increment accumulator 00110001 Data in the accumulator is incremented by one. Carry flag is not affected. ACC ACC+1 Increment register 0001nnn0 Data in the working register Rn is incremented by one. Carry flag is not affected. Rn Rn+1; Rn=R0,R1,R2,R3,R4 for n=0,1,2,3,4
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INC [R1R0] Machine Code Description Operation INC [R3R2] Machine Code Description Operation JAn address Machine Code Description Increment data memory 00001100 Data in the data memory specified by the register pair R1,R0 is incremented by one. Carry flag is not affected. M(R1,R0) M(R1,R0)+1 Increment data memory 00001110 Data memory specified by the register pair R3, R2 is incremented by one. Carry flag is not affected. M(R3,R2) M(R3,R2)+1 Jump if accumulator Bit n is set 100nnaaa aaaaaaaa Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of memory bank remain, if accumulator bit n is set to one. PC (bit 0-10) address, if ACC bit n=1 (n = 0, 1, 2, 3) PC PC+2, if ACC bit n=0 Jump if carry is set 11000aaa aaaaaaaa Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of memory bank remain, if the C (Carry flag) is set to one. PC (bit 0-10) address, if C=1 PC PC+2, if C=0 Direct Jump 1110aaaa aaaaaaaa Bits 0-11 of the program counter are replaced with the directlyspecified address. PC address Jump if carry is not set 11001aaa aaaaaaaa Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of memory bank remain, if the C (Carry flag) is set to zero. PC (bit 0-10) address, if C=0 PC PC+2, if C=1
Operation JC address Machine Code Description
Operation JMP address Machine Code Description Operation JNC address Machine Code Description
Operation
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JNZ A,address Machine Code Description Jump if accumulator is not zero 10111aaa aaaaaaaa Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of memory bank remain, if the accumulator is not zero. PC (bit 0-10) address, if ACC0 PC PC+2, if ACC=0 Jump if register is not zero 10100aaa 10101aaa 11011aaa Description aaaaaaaa aaaaaaaa aaaaaaaa R0 R1 R4
Operation JNZ Rn,address Machine Code
Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of memory bank remain, if the register is not zero. PC (bit 0-10) address, if Rn0; Rn=R0, R1, R4 PC PC+2, if Rn=0 Jump if time-out 11010aaa aaaaaaaa Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of the memory bank remain, if the TF (Timer flag) is set to one. PC (bit 0-10) address, if TF=1 PC PC+2, if TF=0 Jump if accumulator is zero 10110aaa aaaaaaaa Bits 0-10 of the program counter are replaced with the directlyspecified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is zero. PC (bit 0-10) address, if ACC=0 PC PC+2, if ACC0 Move register to accumulator 0010nnn1 Data in the working register Rn is moved to the accumulator. ACC Rn; Rn=R0, R1, R2, R3, R4, for n=0,1,2,3,4
Operation JTMR address Machine Code Description
Operation JZ A,address Machine Code Description
Operation MOV A,Rn Machine Code Description Operation
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MOV A,TMRH Machine Code Description Operation MOV A,TMRL Machine Code Description Operation MOV A,XH Machine Code Description Operation MOV A,[R1R0] Machine Code Description Operation MOV A,[R3R2] Machine Code Description Operation MOV LCDC, A Machine Code Description Operation MOV R1R0,XXH Machine Code Description Move timer to accumulator 00111011 The high nibble data of the Timer counter is loaded to the accumulator. ACC TIMER (high nibble) Move timer to accumulator 00111010 The low nibble data of Timer counter is loaded to the accumulator. ACC TIMER (low nibble) Move immediate data to accumulator 0111dddd The 4-bit data specified by code is loaded to the accumulator. ACC XH Move data memory to accumulator 00000100 Data in the data memory specified by the register pair R1,R0 is moved to the accumulator. ACC M(R1,R0) Move data memory to accumulator 00000110 Data in the data memory specified by the register pair R3, R2 is moved to the accumulator. ACC M(R3,R2) Move accumulator to LCDC register 00110000 Data in the accumulator is moved to the LCDC register. LCDC ACC Move immediate data to R1 and R0 0101dddd 0000dddd The 8-bit data specified by code are loaded to the working registers R1 and R0, the high nibble of the data is loaded to R1, and the low nibble of the data is loaded to R0. R1 XH (high nibble) R0 XH (low nibble)
Operation
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MOV R3R2,XXH Machine Code Description Move immediate data to R3 and R2 0110dddd 0000dddd The 8-bit data specified by code are loaded to the working register R3 and R2, the high nibble of the data is loaded to the R3, and the low nibble of the data is loaded to the R2. R3 XH (high nibble) R2 XH (low nibble) Move immediate data to R4 01000110 R4 XH Move accumulator to register 0010nnn0 Data in the accumulator is moved to the working register Rn. Rn ACC; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4 Move accumulator to RAMB register 00110100 Data in the accumulator is moved to the RAMB register RAMB ACC Move accumulator to ROMB register 00110101 Data in the accumulator is moved to the ROMB register ROMB ACC Move accumulator to timer 00111101 The contents of accumulator is loaded to the high nibble of timer counter. TIMER (high nibble) ACC Move accumulator to timer 00111100 The contents of accumulator is loaded to the low nibble of the timer counter. TIMER (low nibble) ACC 0000dddd The 4-bit data specified by code are loaded to the working register R4.
Operation MOV R4,XH Machine Code Description Operation MOV Rn,A Machine Code Description Operation MOV RAMB, A Machine Code Description Operation MOV ROMB, A Machine Code Description Operation MOV TMRH,A Machine Code Description Operation MOV TMRL,A Machine Code Description Operation
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MOV [R1R0],A Machine Code Description Operation OV [R3R2],A Machine Code Description Operation NOP Machine Code Description OR A,XH Machine Code Description Operation OR A,[R1R0] Machine Code Description Operation OR [R1R0],A Machine Code Description Operation OUT Pi,A Machine Code Description Operation Move accumulator to data memory 00000101 Data in the accumulator is moved to the data memory specified by the register pair R1,R0. M(R1,R0) ACC Move accumulator to data memory 00000111 Data in the accumulator is moved to the data memory specified by the register pair R3, R2. M(R3,R2) ACC No operation 00111110 Do nothing, but one instruction cycle is delayed. Logical OR immediate data to accumulator 01000100 0000dddd Data in the accumulator is logically OR with the immediate data specified by code. ACC ACC OR XH Logical OR accumulator with data memory 00011100 Data in the accumulator is logically OR with the data memory addressed by the register pair R1,R0. ACC ACC OR M(R1,R0) Logical OR data memory with accumulator 00011111 Data in the data memory addressed by the register pair R1,R0 is logically OR with the accumulator. M(R1,R0) M(R1,R0) OR ACC Output accumulator data to port-i 00101101 PA 01001001 PB The data in the accumulator is transferred to the port-i and latched. Pi ACC; Pi=PA or PB
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READ MR0A Machine Code Description Read ROM code of current page to M(R1,R0) and ACC 01001101 The 8-bit ROM code (current page) addressed by ACC and R4 are moved to the data memory M(R1,R0) and accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to accumulator. The address of ROM code are specified as below: Current page (R) ROM code address bit 12~8 ACC (R) ROM code address bit 7~4 R4 (R) ROM code address bit 3~0 M(R1,R0) ROM code (high nibble) ACC ROM code (low nibble) Read ROM code of current page to R4 and accumulator 01001100 The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) are moved to the working register R4 and accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code are specified below: Current page (R) ROM code address bit 12~8 ACC (R) ROM code address bit 7~4 M(R1,R0) (R) ROM code address bit 3~0 R4 ROM code (high nibble) ACC ROM code (low nibble) Read ROM Code of page F to M(R1,R0) and ACC 01001111 The 8-bit ROM code (page F) addressed by ACC and R4 are moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to accumulator. page F (R) ROM code address bit 12~8 are PA3 1111 ACC (R) ROM code address bit 7~4 R4 (R) ROM code address bit 3~0 M(R1,R0) high nibble of ROM code (page F) ACC low nibble of ROM code (page F)
Operation READ R4A Machine Code Description
Operation READF MR0A Machine Code Description
Operation
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READF R4A Machine Code Description Read ROM code of page F to R4 and accumulator 01001110 The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) are moved to the working register R4 and accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to accumulator. page F (R) ROM code address bit 12~8 are PA3 1111 ACC (R) ROM code address bit 7~4 M(R1,R0) (R) ROM code address bit 3~0 R4 high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Return from subroutine or interrupt 00101110 The program counter bits 0~11 are restored from the stack. PC Stack Return from interrupt subroutine 00101111 The program counter bits 0~11 are restored from the stack. The carry flag before entering interrupt service routine is restored. PC Stack C C (before interrupt service routine) Rotate accumulator left 00000001 The contents of the accumulator are rotated one bit left. Bit 3 is rotated to bit 0 and carry flag. An+1 An; An: accumulator bit n (n=0,1,2) A0 A3 C A3 Rotate accumulator left through carry 00000011 The contents of the accumulator are rotated one bit left. Bit 3 replaces the carry bit; the carry bit is rotated into the bit 0 position. An+1 An; An: Accumulator bit n (n=0,1,2) A0 C C A3
Operation RET Machine Code Description Operation RETI Machine Code Description Operation RL A Machine Code Description Operation
RLC A Machine Code Description Operation
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RR A Machine Code Description Operation Rotate accumulator right 00000000 The contents of the accumulator are rotated one bit right. Bit 0 is rotated to bit 3 and carry flag. An An+1; An: Accumulator bit n (n=0,1,2) A3 A0 C A0 Rotate accumulator right through carry 00000010 The contents of the accumulator are rotated one bit right. Bit 0 replaces the carry bit; the carry bit is rotated into the bit 3 position. An An+1; An: Accumulator bit n (n=0,1,2) A3 C C A0 Subtract data memory contents and carry from ACC 00001010 The contents of the data memory addressed by the register pair R1,R0 and the carry are subtracted from the accumulator. Carry is affected. ACC ACC+M(R1,R0)+CF Active SOUND channel with accumulator 01001011 The activated sound begins playing in accordance with the contents of accumulator when the specified sound channel is matched. Turn on sound repeat mode 01001001 00000001 The activated sound plays repeatedly. Turn off sound 01001010 The singing sound will terminate immediately. Turn on sound one mode 01000101 00000000 The activated sound plays only one time.
RRC A Machine Code Description Operation
SBC A,[R1R0] Machine Code Description Operation SOUND A Machine Code Description SOUND LOOP Machine Code Description SOUND OFF Machine Code Description SOUND ONE Machine Code Description
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STC Machine Code Description Operation SUB A,XH Machine Code Description Operation SUB A,[R1R0] Machine Code Description Operation TIMER OFF Machine Code Description TIMER ON Machine Code Description TIMER XXH Machine Code Description Operation XOR A,XH Machine Code Description Operation Set carry flag 00101011 The carry flag is set to one. C1 Subtract immediate data from accumulator 01000001 ACC ACC+XH+1 Subtract data memory contents from accumulator 00001011 The contents of the data memory addressed by the register pair R1,R0 is subtracted from the accumulator. Carry is affected. ACC ACC+M(R1,R0)+1 Set timer stop counting 00111001 The Timer stop counting, when the TIMER OFF instruction is executed. Set timer start counting 00111000 The Timer starts counting, when the TIMER ON instruction is executed. Set immediate data to timer counter 01000111 TIMER XXH Logical XOR immediate data to accumulator 01000011 0000dddd Data in the accumulator is Exclusive-OR with the immediate data specified by code. ACC ACC XOR XH dddddddd The 8 bit data specified by code is loaded to the T imer counter. 0000dddd The specified data is subtracted from the accumulator. Carry is affected.
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XOR A,[R1R0] Machine Code Description Operation XOR [R1R0],A Machine Code Description Operation Logical XOR accumulator with data memory 00011011 Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair R1,R0. ACC ACC XOR M(R1,R0) Logical XOR data memory with accumulator 00011110 Data in the data memory addressed by the register pair R1,R0 is logically Exclusive-OR with the accumulator. M(R1,R0) M(R1,R0) XOR ACC
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright a 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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